Browsing All posts tagged under »verilog«

New release of Icarus Verilog

September 28, 2010


Icarus Verilog is a compiler and simulator for one of the most used Hardware Description Language (Verilog of course). Today the developers released version 0.9.3; here is the announce on their SourceForge page. The Release Notes state that, other than bug fixes, the current implementation is becoming closer to the standard specifications. This new version […]

Debugging OpenRisc software inside RTL simulation

August 7, 2010


Using Icarus Verilog and a custom built GDB to debug software running inside a simulation of a OpenRisc System On Chip, thanks to the Verilog Procedural Interface.

New OpenRISC: academic work helps open source hardware

July 1, 2010


OpenCores delivered a new version of OpenRISC, an open source processor hosted together with many open source hardware projects; more information on their current news page. What is special about this version is that the major driver for the code development has been an academic thesis on verification. Waqas Ahmed of the Royal Institute of […]

MyHDL on Ubuntu

February 23, 2010


The MyHDL Python modules can now be installed on Ubuntu using a convenient Launchpad PPA repository.

Languages for hardware development

January 14, 2010


A subjective view on some hardware description languages.

OpenRisc Verilog simulation of serial port communication

December 17, 2009


An explanation of how to test an OpenRisc architecture with a hardware/software co-simulation; all the used tools are open source.