Browsing All posts tagged under »orsoc«

OpenRisc Verilog simulation of serial port communication

December 17, 2009


An explanation of how to test an OpenRisc architecture with a hardware/software co-simulation; all the used tools are open source.

OpenRisc simulator runs Linux

December 6, 2009


OpenCores is an organization owned by ORSoc that invests in open source hardware. Their site hosts many hardware projects that ship the source code (Hardware Description Language in this case) with the GNU Lesser General Public Licence. This allows the adoption of free Intellectual Properties (hardware blocks) in any hardware design, being it proprietary (closed-source) […]


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