What is special about this version is that the major driver for the code development has been an academic thesis on verification. Waqas Ahmed of the Royal Institute of Technology published a dissertation on some functional and formal methods for hardware verification, using an OpenRISC1200 architecture as the system under test. The experiments led to the discovery of many bugs and errors that have been promptly corrected in this version of the core.
Linus’ law states that “given enough eyeballs, all bugs are shallow”. This has not been the case for open source hardware yet, because of the low number of developers (and users) involved with respect to the open source software world. While the software ecosystem thrives on large number of developers, the hardware one needs quality above all, for many reasons. One specific example comes to mind these days:
- When the operating system of a phone is buggy, the problem can be solved with the small cost of a remote update.
- When the antenna of a phone is faulty (for example it receives poorly if held with your left hand), you can see the effects in the news.
The quality of the contribution to open source hardware projects must be kept high. Another example is Aeroflex Gaisler that provides open source cores (the LEON series) and IPs. They enforce good code practices and are able to create space-grade products that are used in applications where an error can blow up millions of dollars.
What happened with OpenRISC is that the project benefited from its open nature while giving the academic world an opportunity for growth and education. The quality of the academic contribution is very high, and from another point of view the learning challenge that a complex system such as OpenRISC offers to students is appealing.
Once the universities around the world start to invest on open source hardware to the point that they improve hardware quality and performance to the level of commercial products, then the industry will have a cheap alternative to the now very expensive (but reliable and cutting-edge) IP portfolio offered by the major houses.
The full document of OpenRISC verification is available for OpenCores users on the download page; the process involves both SystemC and SystemVerilog, and is based on the Open Verification Methodology (OVM).